Digital VLSI Systems on Chip

Today's large-scale digital integrated circuits and systems-on-a-chip, such as modern general processing units (GPUs), can contain >50 billion transistors. Two things were instrumental in enabling this massive scalability: electronic design automation (EDA) tools and intellectual property (IP) blocks allowing for hierarchical design.

In this course, you will learn how to use such EDA tools and IP blocks to go from the register-transfer level (RTL) description of your digital design to a final layout that is clean for tapeout and meets your specifications. To do so, you will also learn about power/performance/area tradeoff optimization, hardware-algorithm co-design, and memory hierarchy.

These tools and concepts will be practiced and applied in a project, in which you will explore and apply your own design choices to meet a well-defined design target in a digital system-on-chip.

The final course grade consists of two parts:

• Project (50% of the total grade). When G be the group grade for the final design report report (scale of 10), P is the possible adjustment made by a peer review (-1 <= P <= 1). The individual grade for the project part is thus computed as G+P.

• Individual written exam (50% of the total grade).

The results of the two parts must have been obtained within the same academic year, and students must have a grade of 5.8 or higher for both the final design report and the individual written exam to pass the course.

In case the final design report is failed, two repair options exist for the associated 50% of the total grade:

• if the project grade for the group is insufficient, another group assignment will be provided (maximum score for this assignment: grade 8);

• if the project grade was not received by a student due to dropping out from the project or not contributing sufficiently, an individual assignment will be provided (maximum score for this assignment: grade 8).

In case the individual written exam is failed, a resit individual written exam must be taken for the associated 50% of the total grade.

Disclaimer: information may change depending on unforeseen circumstances or measures (see: TER Art 29, sub 4).