Digital VLSI Systems on Chip

Today's large-scale digital integrated circuits and systems-on-a-chip, such as modern general processing units (GPUs), can contain >50 billion transistors. Two things were instrumental in enabling this massive scalability: electronic design automation (EDA) tools and intellectual property (IP) blocks allowing for hierarchical design.

In this course, you will learn how to use such EDA tools and IP blocks to go from the register-transfer level (RTL) description of your digital design to a final layout that is clean for tapeout and meets your specifications. To do so, you will also learn about power/performance/area tradeoff optimization, hardware-algorithm co-design, and memory hierarchy.

These tools and concepts will be practiced and applied in a project, in which you will explore and apply your own design choices to meet a well-defined design target in a digital system-on-chip.