Digital Systems A

In this course, you will learn as student the basics of digital systems. You will learn to design, simulate, build and emulate custom and standard digital circuits. To be able to accomplish the above, you will get familiar with several hardware related topics including, among other things, the overall design of computer systems, data representation in computers, boolean algebra, logic minimization, sequential circuits, Finite State Machines, and standard modules such as multiplexers, registers, etc.. In addition, you will also get an introduction to the hardware description language SystemVerilog and use it during practical lab sessions.

Topics are:

• Introduction to digital design: representation, numbers

• Boolean algebra

• Logic minimization

• Sequential circuits and FSMs

• Standard modules (multiplexers, decoders, ROM, registers, counters, etc.)

• Digital implementation technology (CMOS gates)

• SystemVerilog: structural, behavioral, testbenches, simulation

2 written partial exams, 1 re-exam, course lab assignments.

In addition, there will be a test in week 4 and week 8.

The result of the tests is expressed as R, ranging 0 to 10. The R figure is the average of the results of all the tests, in which a non-made test results into a 0.

The results of the two partial exams are averaged. This gives the exam grade T.

The final grade of C of the course is then calculated as follows:

C = T + R x (10-T) / 100.

This calculation is done with one decimal accuracy, and the final grade will be rounded up to half.

The result of the on-line tests, R, is valid for the partial exams and the resit, but only in the year the on-line tests have been made.

The final mark is valid only when all course lab assignments have been successfully completed.

The resit includes the contents of both partial exams.

The result of the partial exams expires for the resit and is not transferable to the next academic year.

In case of insufficient results for the course labs, a repair option may exist in accordance with Article 2 Exameneisen, Clause 4, of the Uitvoeringsregeling 2024-2025.

Disclaimer: information may change depending on unforeseen circumstances or measures (see: TER Art 29, sub 4).