Processor Design Project

This is an integration course designed to enable students to apply their knowledge of computer architecture and computer engineering to enhance the design of a general-purpose processor. The primary objective is to improve the performance of a RISC-V + LLVM-based computing platform, with a focus on both architectural and compiler-related aspects.

At the start of the course, students are provided with two resource packages:

1. A RISC-V System-on-Chip (SoC) implementation in Verilog, a curated set of benchmarks from the GMPbench and MiBench suites, and all supporting files required for simulation and FPGA deployment.

2. An archive containing the LLVM RISC-V cross-compiler toolchain.

To assess and validate their design improvements, each student group is equipped with a Zynq-7000 FPGA board, which serves as the target platform for implementation and benchmarking.

To successfully complete the course, students are required to:

1. Complete two parts of a guided laboratory assignment;

2. Submit an intermediate report outlining their intended approach and planning;

3. Submit a final report describing the implemented design and providing an analysis of the results, following the published grading criteria.

The final individual grade is determined based on:

• A group grade, derived from the quality of the final and intermediate reports, and

• A peer review process within each group, assessing individual contributions.

Throughout the quarter, students are expected to provide regular progress updates. These updates are used to offer high-level guidance and ensure students stay on track toward achieving their design objectives.

If the final result is insufficient, repair options may be available in accordance with Article 17A (Times and number of examinations, paragraph 1) of the Teaching and Examination Regulations (TER).

Disclaimer: Course requirements and procedures are subject to change due to unforeseen circumstances or institutional decisions (see TER, Article 2, paragraph 5).